1. Field of the Invention
The present invention relates to the implementation of memory access interfaces suitable for multimedia processors.
2. Description of the Related Art
Many computer and multimedia systems require memory access interfaces permitting the transfer of data to and from memory, as well as additional control functions that may be required. This memory may be used to store temporary variables, control information, frame memories for picture storage, and other requirements of the system. Control functions for such memories may include initialization, refresh and memory bank overlapping, also known as ping-ponging. Speed of data transfer and efficiency of data transfer are typically high priorities in such systems. Consumer multimedia systems and computer systems require high performance access to memories. Often, to ensure minimum cost of the system, the memories are operated very close to their optimal bandwidth. In other words, less expensive memory is typically lower performance, so to reduce system costs, developers use inexpensive memories and try to operate them as close as possible to their upper performance limit.
To approach this upper performance limit, typically complex memory access interfaces are used. For example, DRAM semiconductor memory access requires a RAS cycle to set the row address before successive column addresses for that row can be set to initiate data transfers. By using two or more banks of DRAMs, one bank can perform a RAS cycle while another performs data transfers. This concept is formalized by the use of SDRAM which is designed for such bank ping-ponging (for example, see NEC uPD4516161G5-A12-7JF specifications for 16 Mbit SDRAM).
To reduce complexity and cost of implementing memory access interfaces, the easiest way is to match the internal process timing to the external memory type or configuration. For example, in an MPEG-2 (see "IS 13818--Generic Coding of Moving Pictures and Associated Audio" by International Organization for Standardization, ISO MPEG Document, ISO-IEC/JTC1/SC2/WGI11 1994) video decoder integrated circuit using SDRAM as it's frame store, the motion compensation process which reads motion compensated macro-block pixel information from the SDRAM may generate row and column addresses with a timing similar to that required by the SDRAM. Thus, ping-ponging of banks is achieved by the motion compensation process. Matching internal process timing to the external memory type usually ties the internal architecture to the type or configuration of the external memory used. Thus, the internal generation of addresses by each internal process is designed specifically for a particular memory type or configuration.
There are several problems which this invention solves. An object of this invention is to permit memory accesses to occur sequentially as close together as possible in order to maximize the performance of memory accesses. Some memory systems require some kind of preprocessing to occur before the data transfer of a memory access can occur. For example, DRAM semiconductor memories require RAS and CAS cycles to initiate memory accesses. In a system with multiple DRAMs, it is possible to overlap in time the RAS cycles of one or more DRAMs with the CAS cycles of other DRAMs. Another example is SDRAM which contains multiple banks allowing for the overlap of one bank preprocessing with another banks data transfers. The control and optimization of timing for this overlap may result in complicated memory access controllers with complicated interfaces to the processes requiring access to the memory. An object of this invention is the implementation of a memory access controller with simple interfaces to processes requiring high performance access to memories. An object of this invention is the isolation of the processes requiring memory access from the control of the memory itself.